Field
The present disclosure relates generally to electronics, and more specifically to the operation and design of stacked metal oxide semiconductor (MOS) and metal oxide metal (MOM) capacitors.
Background
Metal oxide semiconductor (MOS) capacitors and metal oxide metal (MOM) capacitors are used in many applications, such as in analog filters. A structure referred to as a stacked capacitor (stackcap) can comprise both MOS and MOM capacitors.
MOS capacitors, also may be referred to as metal oxide semiconductor varactors (MOSVARS) of either N- or P-type, having a capacitance which varies with applied voltage across their terminals. MOM capacitors comprise a dielectric, oxide, or insulating layer between two or more metal layers and include, but are not limited to, flux capacitors, fractal capacitors, parallel-plate capacitors, and woven capacitors.
MOS capacitors are generally more area efficient than MOM capacitors and therefore can be used in place of or in conjunction with MOM capacitors in a stackcap architecture to save circuit area. For example, the ratio of capacitance to area can be more than four times greater for a MOS capacitor than for a MOM capacitor. Unfortunately, MOS capacitors may exhibit non-linearity caused by capacitance variation with respect to voltage, the non-linearities of MOS capacitors being significantly greater than non-linearities exhibited by MOM capacitors.
Certain foundries and processes may allow vertical or other means of integration of both a MOS capacitor and MOM capacitor, allowing fabrication of the stackcap. A stackcap generally has a very dense architecture as it combines the area density of both the MOM capacitor and MOS capacitor and accordingly consumes a small amount of circuit area. Unfortunately, when used in high-density circuit applications, use of the stackcap may lead to non-linearities and may prevent a stackcap-only capacitor implementation, and may lead to the need for, or substitution of, additional MOM capacitance to achieve better linearity.
Therefore, a stacked MOS/MOM capacitance with improved linearity that minimizes circuit area is desirable.